1. Field of the Invention
The present invention relates to a method for forming a semiconductor device and, more particularly, to a method for forming a semiconductor device that has non-volatile memory cells, high-voltage CMOS transistors, and low-voltage, deep sub-micron CMOS transistors on the same substrate.
2. Description of the Related Art
A non-volatile memory cell is a semiconductor device that stores information even after power has been removed from the device. Two of the most common types of non-volatile memory cells are electrically-erasable programmable read-only-memory (EEPROM) cells and flash memory cells.
EEPROM and flash memory cells are commonly formed on the same substrate as high-voltage CMOS transistors as both memory cell types are electrically programmed and erased with voltages that are typically much larger than the voltages required to read the cells.
In addition, although less common, EEPROM and flash memory cells, along with the high-voltage transistors, are also formed on the same substrate as low-voltage, deep sub-micron (e.g., 0.25 microns and below) CMOS logic transistors.
One problem with forming non-volatile memory cells, high-voltage CMOS transistors, and low-voltage, deep sub-micron CMOS logic transistors on the same substrate is that two sets of low-voltage device parameters must be maintained if a logic circuit, which is formed from the low-voltage logic transistors, is to be formed both with and without the non-volatile memory cells.
The two sets of parameters must be maintained because in one case the logic circuit is formed in a low-voltage CMOS process while, in the other case, the logic circuit is formed in a hybrid process which must also accommodate the fabrication requirements of the memory cells and the high-voltage transistors.
FIGS. 1A-1J show cross-sectional drawings that illustrate a conventional process for forming a non-volatile memory cell, high-voltage CMOS transistors, and low-voltage, deep sub-micron CMOS transistors on the same substrate.
As shown in FIG. 1A, the process begins with a wafer 100 which is conventionally formed to have a substrate 110, spaced-apart field oxide regions FOX which are formed in substrate 110, and a layer of sacrificial oxide 112 which is formed on the top surface of substrate 110 between the field oxide regions FOX.
With wafer 100, the process continues by forming and patterning a first implant mask 114 on the surface of wafer 100 which defines a high-voltage n-well region 116. Once mask 114 has been formed, region 116 of wafer 100 is implanted with a n-type dopant, such as phosphorous, to form a high-voltage n-well 120. The implant energy and dose of a phosphorous implant for a high-voltage n-well are typically in the range of 120 to 400 KeV and 1.times.10.sup.11 to 1.times.10.sup.13 atoms/cm.sup.2.
Following the formation of n-well 120, a n-type dopant, such as phosphorous, is implanted into n-well 120 to form a punchthrough prevention region (not shown) below the surface of n-well 120. The implant energy and dose of a phosphorous punchthrough implant are typically in the range of 20 to 90 KeV and 1.times.10.sup.11 to 1.times.10.sup.13 atoms/cm.sup.2.
Next, a n or p-type dopant (depending on the poly doping type) is implanted into n-well 120 to set the threshold voltages of the to-be-formed high-voltage p-channel transistors. The implant energy and dose of a boron threshold voltage implant are typically in the range of 10 to 30 KeV and 1.times.10.sup.11 to 1.times.10.sup.13 atoms/cm.sup.2. Once the threshold voltages of the high-voltage p-channel transistors have been set, first implant mask 114 is removed. The photoresist strip may be followed by an optional n-well thermal drive-in step.
After this, as shown in FIG. 1B, a second implant mask 122 is formed and patterned on the surface of wafer 100 to define a p-well region 124. Once mask 122 has been formed, region 124 is implanted with a p-type dopant to form a high-voltage p-well 126. P-well 126, in turn, includes a high-voltage region 126A and an array region 126B. The implant energy and dose of a boron implant for a high-voltage p-well are typically in the range of 90 to 250 KeV and 1.times.10.sup.11 to 1.times.10.sup.13 atoms/cm.sup.2.
Following the formation of p-well 126, a p-type dopant is implanted into p-well 126 to form a punchthrough prevention region (not shown) below the surface of p-well 126. The implant energy and dose of a boron punchthrough implant are typically in the range of 70 to 150 KeV and 1.times.10.sup.11 to 1.times.10.sup.13 atoms/cm.sup.2.
Next, a p-type dopant is again implanted into p-well 126 to set the threshold voltages of the to-be-formed high-voltage n-channel transistors. The implant energy and dose of a boron threshold voltage implant are typically in the range of 10 to 60 KeV and 1.times.10.sup.11 to 1.times.10.sup.13 atoms/cm.sup.2. Once the threshold voltages of the high-voltage n-channel transistors have been set, second implant mask 122 is removed. The photoresist strip may be followed by an optional p-well thermal drive-in step.
Following this, as shown in FIGS. 1C-1D, the same sequence of events is generally repeated to form a plurality of low-voltage wells. Specifically, as shown in FIG. 1C, a third implant mask 130 is formed and patterned to define a low-voltage n-well region 132 on the surface of wafer 100. Once mask 130 has been formed, region 132 of wafer 100 is implanted with a n-type dopant to form a low-voltage n-well 134. The implant energy and dose are typically the same as those used to form n-well 120.
Following the formation of n-well 134, a n-type dopant is optionally implanted into n-well 134 to form a punchthrough prevention region (not shown) below the surface of n-well 134. The implant energy and dose are typically the same as those used with the high voltage devices.
Next, a n-type dopant is again implanted into n-well 134 to set the threshold voltages of the to-be-formed low-voltage p-channel transistors. The implant energy and dose are typically the same as those used with the high voltage devices. Once the threshold voltages of the low-voltage p-channel transistors have been set, third implant mask 130 is removed. The photoresist strip may be followed by an optional n-well thermal drive-in step.
Next, as shown in FIG. 1D, a fourth implant mask 136 is formed and patterned on the surface of wafer 100 to define a low-voltage p-well region 140. Once mask 136 has been formed, region 140 is implanted with a p-type dopant to form a low-voltage p-well 142. The implant energy and dose are typically the same as those used to form p-well 126.
Following the formation of p-well 142, a p-type dopant is optionally implanted into p-well 142 to form a punchthrough prevention region (not shown) below the surface of p-well 142. The implant energy and dose are typically the same as those used with the high voltage implants.
Next, a p-type dopant is again implanted into p-well 142 to set the threshold voltages of the to-be-formed low-voltage n-channel transistors. The implant energy and dose are typically the same as those used with the high voltage implants. Once the threshold voltages of the low-voltage n-channel transistors have been set, fourth implant mask 136 is removed. The photoresist strip may be followed by an optional p-well thermal drive-in step.
Following this, as shown in FIG. 1E, sacrificial oxide layer 112 is removed. This is followed by the growth of a layer of high-voltage gate oxide 144 on n-well 120, p-well 126, n-well 134, and p-well 142. High-voltage gate oxide layer 144 is formed to be about one-half to two-thirds of its final thickness.
Once gate oxide layer 144 has been formed, a first protect mask 146 is formed and patterned to protect n-well 120 and high-voltage region 126A of p-well 126. Following this, the unmasked regions of gate oxide layer 144 are removed to expose the surface of substrate 110.
After this, as shown in FIG. 1F, protect mask 146 is stripped. Following this, a layer of tunnel oxide 150 is grown on array region 126B, n-well 134, and p-well 142. The formation of tunnel oxide layer 150 also causes high voltage gate oxide layer 144 to increase to its final thickness.
Next, a layer of polysilicon (poly-1) 152 is formed on field oxide region FOX, gate oxide layer 144, and tunnel oxide layer 150. Poly-1 layer 152, which is utilized to form the floating gates of the memory transistors and the gates of the high-voltage transistors, is then doped. After poly-1 layer 152 has been deposited and doped, a second protect mask 154 is formed to cover n-well 120 and p-well 126, and expose n-well 134 and p-well 142.
Following this, as shown in FIG. 1G, the unmasked portions of poly-1 layer 152 are removed to expose the surface of the portion of tunnel oxide layer 150 which is formed over n-well 134 and p-well 142. Next, mask 154 is removed, and a layer of interpoly dielectric 156 is formed over the exposed field oxide regions FOX, the top surfaces of tunnel oxide layer 150, and poly-1 layer 152. Dielectric layer 156 is commonly formed from layers of oxide-nitride-oxide (ONO).
Next, a third protect mask 160 is formed to cover n-well 120 and p-well 126, and expose n-well 134 and p-well 142. Following this, as shown in FIG. 1H, the unmasked portions of dielectric layer 156 and tunnel oxide layer 150 are removed to expose the surface of n-well 134 and p-well 142. After this, mask 160 is removed.
To insure that all of the tunnel oxide layer 150 has been removed, wafer 100 is then cleaned. In addition to removing any remnants of tunnel oxide layer 150, the cleaning step also removes a portion of the top layer of oxide of interpoly dielectric layer 156. As a result, the top layer of oxide of interpoly dielectric layer 156 must be thick enough to allow a portion of the top layer of oxide to be removed.
Following this, a layer of gate oxide 162 is formed on n-well 134 and p-well 142. Once gate oxide layer 162 has been formed, a second layer of polysilicon (poly-2) 164 is formed on the exposed field oxide regions FOX, interpoly dielectric layer 156, and gate oxide layer 162. Poly-2 layer 164, which is utilized to form the control gates of the memory transistors and the gates of the low-voltage logic transistors, is then doped. (Optionally, poly-2 layer 164 may also be doped when the source and drain implants are performed).
Next, as shown in FIG. 1I, a first definition mask 166 is formed and patterned on poly-2 layer 164 to initially define a stacked-gate memory transistor 170, a n-channel low-voltage transistor 172, and a p-channel low-voltage transistor 174. Once mask 166 has been formed, the unmasked areas of poly-2 layer 164 are etched until poly-2 layer 164 has been removed.
After this, as shown in FIG. 1J, mask 166 is hardened, and a second definition mask 176 is formed and patterned on dielectric layer 156 to define a n-channel high-voltage transistor 180, and a p-channel high-voltage transistor 182. In addition, as further shown in FIG. 1J, mask 176 also covers the low-voltage portion of wafer 100.
Once mask 176 has been formed, the unmasked areas are etched until dielectric layer 156 and poly-1 layer 152 have been removed. After this, conventional steps are followed.
Thus, as shown in the above steps, low-voltage wells 134 and 142 go through a number of fabrication steps, such as the deposition and removal of poly-1 layer 152 and dielectric layer 156, and the growth of oxide layers 144 and 150, which would not be present is a process that did not form memory and high-voltage transistors. Unfortunately, these additional steps alter the device parameters.
Thus, there is a need for a method of forming a semiconductor device that has memory cells, high-voltage CMOS transistors, and low-voltage, sub-micron CMOS transistors such that the device parameters of the low-voltage transistors are the same regardless of whether the memory cells and high-voltage transistors are formed with the low-voltage transistors.